Nodes, EUV tools, yield, and the push toward angstrom‑class manufacturing.
An article joins this feed when it matches these terms. Each one is also a search of its own.
That is the honest shape of this release: a paper, a repo, a checkpoint, and an evaluation table that claims to beat Claude Opus 5. Everything below is either read directly out of the repository or labelled as the vendor's own…
The development is particularly relevant to chipmakers and foundries moving toward High-NA EUV lithography, where increasingly complex patterns demand significantly more computing power. It could also help European semiconductor manufacturers improve production efficiency and accelerate the introduction of advanced AI…
Semiconductor watchers are tracking signs that ASML is developing a die-to-wafer hybrid bonding tool, a move that could deepen its ties with chipmakers and challenge packaging specialist Besi. The technology promises tighter alignment, cleaner processing and a more flexible route…
Next generation of semiconductor manufacturing will be enabled by the precise interaction of many highly complex process steps. ZEISS NLX: Makes internal structures in modern chip packages visible without destroying them. Chip manufacturers can use it, as an example, to…
Without acceleration, these essential techniques are often too slow for full-chip, manufacturing-scale deployment, and forcing engineering teams to make trade-offs between optimization depth and project schedules. This creates a risk of lithographic hotspots and reduced process margins, which can impact…
The agreement was signed at the Mimos Technology Preview 2026 in Kuala Lumpur and witnessed by Mohammad Yusof Apdal, deputy minister of science, technology and innovation, and Saat Shukri Embong, president and group CEO of Mimos Bhd. MTSB, the commercialisation arm…
As it becomes harder and costlier to shrink transistors, advanced packaging has become the place chip equipment makers look to for their next leg of growth, and ASML appears to be preparing its second move into it. Patent filings analyzed…
ASML has not announced anything yet, but its patent filings, a news report and its own roadmap all suggest so. We believe it will start with a die-to-wafer (D2W) hybrid bonding (HB) tool. This is harder to build than wafer-to-wafer but…
Online profitability calculators are handy, but they hide the logic. If you understand the six formulas underneath, you can sanity check any calculator, any ranking and any sales pitch. This is a step-by-step walkthrough you can build in a spreadsheet…
The nanostack architecture reconfigures transistor arrangement, allowing for the stacking of nanosheets and a departure from traditional two-dimensional scaling limitations. IBM’s approach fundamentally alters how transistors are built, moving beyond the established X and Y axes to incorporate the Z…